Abstract
Electronic Design Automation (EDA) tooling facilitates the development of cutting edge technologies at the nanometre scale, providing the means to rationalise an incredibly complex task into abstractions simple enough to become second nature to an engineer. In a post-Moore’s Law environment, an increasing number of companies are turning to bespoke Application-Specific Integrated Circuits (ASICs) to achieve the same generational performance gains that consumers have come to expect. The extreme costs of a failed tape-out rightly demands high levels of assurance from verification and physical analysis, leading to long development timescales. From our personal experience (not to mention that of our colleagues), companies tend to develop layers of internal tooling and processes around the major EDA vendors’ offerings to help reduce these risks.
However, this raises a question of if there is a missing piece of the puzzle? Our intention with this paper is to properly describe this “missing piece” and highlight some of the issues with current EDA tooling that make it difficult for engineering teams to fill it in. We then propose some potential solutions that could improve the situation for users and vendors alike.
