RISC-V & Chips Alliance Summit

Author: Ben Packman
Topic: Comment, Events, News

This year’s two-day RISC-V Summit brought together innovators, academics and business leaders to address developments in the RISC-V ecosystem, as well as discuss future partnerships and commercialization opportunities.

Representing PQShield in sunny San Jose, California, was VP of Engineering, Graeme Hickey. And as well as his many discussions with individuals keen to learn more about our cybersecurity products and credentials, he found time to take in a number of keynotes, technical tracks and tutorials.

Here’s what he had to say…

RISC-V Summit

The event floor had some great demos and booths including SiFive, Zephr, lowRISC and MicroChip.

Microsoft presented Caliptra which is their open source Root of trust subsystem providing similar functionality to the OpenTitan offering from Google. And the Antmicro team presented their work on the open source simulator Verilator, making it compatible with UVM – the standard verification framework.

We also attended a fantastic one-day workshop with open hardware consortium Chips Alliance.

Day 1 Talks

SERV: 32-bit is the New 8-bit – Olof Kindgren, Qamcom

This was an interesting talk on the smallest possible implementations of RISC-V CPUs. It’s potentially relevant to our own platform security product family, where IP is an important KPI.

The RISC-V Vector Cryptography Extensions – G. Richard Newell, Microchip Technology Inc. & Ken Dockser, Rivos Inc.

A status update was provided on the Crypto vector extension proposal. This includes dedicated Crypto Vector instructions for AES, SHA2, GHASH, SM4 and SM3 and, additionally, generic vector bit manipulation instructions which can be used across different crypto algorithms. The extension is in the final stages of ratification.

Day 2 Talks

HW-SW Co-development for RISC-V Based Secure ML Systems with the Sparrow Project and Renode – Michael Gielda, Antmicro & Kai Yick, Google

Interesting talk on how Antmicro has been working with google using renode. We’ve been partnering with antimicro on this tool, and it was good to see how it can be used in a variety of use cases.

RISC-V Zkt: Portable Timing Attack Resistance (via Dynamic Taint Analysis) – Markku-Juhani O. Saarinen, PQShield Ltd

A brilliant talk from our very own Markku Saarinen, outlining the constant time ISA extension and implementation of a simulator to prove timing attack resistance. Great to see the talk was well received by the audience.

The OpenTitan Project – Dom Rizzo, Google

A status update on the OpenTitian root of trust from Google. This sits in the same area as the IP we’re currently developing, and they did in fact mention adding support for PQC (albeit initially in the form of Hash-based schemes).

Introducing RISC-V Confidential Computing for IoT Devices – Bicheng Yang & Dingji Lee, Shanghai Jiao Tong University

Interesting talk on a RISC-V TEE implementation, showing comparison with existing industry solutions such as ARM Trustzone and Intel SGX. Included was a demonstration of a reference platform for secure IoT solutions using RISC-V TEE.

Confidential Computing for RISC-V-based Platforms – Ravi Sahita, Rivos Inc.

Another insightful talk on confidential computing using RISC-V TEE implementation on an SoC.

What an event! Many thanks to everyone who presented, shared insights or simply approached the PQShield team to talk about all things PQC. We hope to be crossing paths with you again in 2023.