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SPOTLIGHT PUBLICATION | 22/05/2025

Your Hardware Refresh Is a Quantum Deadline with Mamta Gupta, Lattice Semiconductor

In this episode of Shielded, Johannes Lintzen sits down with Mamta Gupta of Lattice Semiconductor to explore how hardware-rooted security must evolve to meet the post-quantum challenge.

HSMs and PQC Migration: Are We There Yet? / RSA

In this special RSA 2025 edition we gather 4 leading voices from the world of hardware security to discuss a cornerstone technology powering the post-quantum migration: the Hardware Security Module (HSM).

Awareness to Action: The Blueprint for Quantum-Resilient Security | Garfield Jones

In this episode of Shielded: The Last Line of Cyber Defense, host Johannes Lintzen sits down with Dr. Garfield Jones from CISA to dive into the practical steps for post-quantum migration, making the case that waiting until 2035 is far too late.

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WiP: Applicability of ISO Standard Side-Channel Leakage Tests to NIST Post-Quantum Cryptography

We discuss how to apply ISO 17825 to hardware modules that implement lattice-based PQC standards for public-key cryptography. We find that simple “random key” vs. “fixed key” tests are unsatisfactory due to the close linkage between public and private components of PQC keypairs.

SP 800-22 and GM/T 0005-2012 Tests: Clearly Obsolete, Possibly Harmful

NIST SP 800–22, describes 15 statistical tests and suggests that they can be used to evaluate random and pseudorandom number generators in cryptographic applications. The Chinese standard GM/T 0005–2012 describes similar tests. These documents have not aged well. The weakest pseudorandom number generators will easily pass these tests, promoting false confidence in insecure systems.

More efficient, provably-secure direct anonymous attestation from lattices

The Cloud-Edges (CE) framework, wherein small groups of Internet of Things (IoT) devices are serviced by local edge devices, enables a more scalable solution to IoT networks.

On Entropy and Bit Patterns of Ring Oscillator Jitter

We show how to evaluate entropy, autocorrelation, and bit pattern distributions of thermal jitter ring oscillator noise sources, even with low jitter levels or some bias.

Development of the RISC-V entropy source interface

The RISC-V true random number generator (TRNG) architecture breaks with previous ISA TRNG practice by splitting the entropy source (ES) component away from cryptographic DRBGs.

MIRACLE: MIcRo-ArChitectural Leakage Evaluation: A study of micro-architectural power leakage across many devices

In this paper, we describe an extensible experimental infrastructure for evaluating the micro-architectural leakage, based on power consumption, that stems from a physical device.

A Concrete Treatment of Efficient Continuous Group Key Agreement via Multi-Recipient PKEs

Continuous group key agreements (CGKAs) are a class of protocols that can provide strong security guarantees to secure group messaging protocols such as Signal and MLS.

A lightweight ISE for ChaCha on RISC-V

This paper proposes a lightweight ISE to support the cipher ChaCha on RISC-V architectures. we target embedded computing systems such as IoT edge devices that don’t support a vector engine.

XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage

Side-channel analysis (SCA) attacks pose a major threat to embedded systems due to their ease of accessibility.

An Instruction Set Extension to Support Software-Based Masking

In both hardware and software, masking can represent an effective means of hardening an implementation against side-channel attack vectors such as Differential Power Analysis (DPA).

Probing Security through Input-Output Separation and Revisited Quasilinear Masking

This paper introduces a new framework for the composition of probing-secure circuits.

SoK: How (not) to Design and Implement Post-quantum Cryptography

Post-quantum cryptography has known a Cambrian explosion in the last decade. We systematize the current state of knowledge on post-quantum cryptography.