Maximizing Resources with Lattice and Hash
Many ASICs already comprise a SHA-3 accelerator, but haven’t been designed for lattice-based cryptographic algorithms, such as FIPS 203 ML-KEM and FIPS 204 ML-DSA.
The lattice-based algorithms can add significant area – which is critical to the design and capability of embedded devices. It can be a challenge to integrate lattice-based and hash-based PQC while maintaining a small area.
PQPlatform-Lattice
PQPlatform-Lattice supports side-channel-protected ML-KEM and ML-DSA, and can offload the SHA-3 functionality to firmware to keep hardware resources minimal.
